A brief look at silicon

Through the recent announcement that GlobalFoundaries joined Google's open source silicon initiative, that Google had an open source silicon initiative. It turns out that Google wants to be what GNU was for FOSS, except for silicon. Furthermore they are funding some people to make chips of their own.

Tooling

Coming at this in a somewhat backwards way we're going to look at the tooling that is used for silicon design, and hopefully work backwards from there.

Open Source PDK's

Google maintains a handful of process design kits (PDKs). A PDK is a set of files used within the industry ^1. A typical PDK has a primitive device library, verification decks, technology data, rule files, simulation models of primitive device, and design rule manual.

SKY130

The SkyWater Open Source PDK is a PDK that targets the SKY130 process node at the moment. Though, they are saying if this goes well then more advanced nodes will be developed. They currently have an experimental preview. Currently they have documentation, electronic design automation(EDA) tool with multiple files supported, primitive cell libraries and models for analog designs, multiple digital cell libraries, and they also have multiple examples.^2

GF180MCU

Similarly the GlobalFoundries GF180MCU is an open source PDK that enable designs to be manufactured for their GF180MCU process node. They currently have an experimental preview. Briefly looking at the docs, it seems like they have some analog, digital, and physical verification.^3

OpenLane

"OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout, and a number of custom scripts for design exploration and optimization."^4

XLS

XLS stands for Accelerated HW Synthesis, and is experimental. The idea is that you design hardware via High Level Synthesis (HLS) toolchain, and the focus is to co-design hardware to software and vice versa.^5

Hardware Description Language(HDL) rules for Bazel

Bazel seems to be a high-level build language/system. This repository seems to be the connection between whatever language you are using to describe hardware and the fully placed and routed design. Think of it like make, but for silicon.^6

Verible

It's a SystemVerilog parser.^7

CFU Playground

The Custom Function Unit(CFU) Playground is a collection of software, gateware, and hardware configured to make ML and adapting designs a bit easier. ^8

Notes

It seems like file formatting for the various manufacturers is a bit tricky.

Questions

What is an EDA tool?

Is a software tool that allows for designing integrated circuits and printed circuit boards.^9

What is a process node?

Refers to a specific semiconductor manufacturing process and its design rules. ^10

What does physical verification entail?

It is where some EDA software ensures correct electrical and logical functionality along with its manufacturability.^11

What is RTL

Stands for Register Transfer Level, and it is an abstraction for defining the digital portions of a design.^12

What is GDSII

Is a binary database file format that is a standard for EDA data exchange for integrated circuit(IC) or IC layout artwork.^13

What is OpenROAD

It is a project that is trying to lower barriers of cost, expertise, and uncertainty of hardware design.^14 Pretty cool!

What is Yosys

Framework for RTL synthesis tool. ^15

What is Magic

It is a VLSI layout tool written in Tcl.^16

What is Netgen

It seems like a multiphysics finite element simulator?^17

What is CVC

Maybe something fancy? ^18

What is SPEF-Extractor

Reads LEF and DEF files and generates SPEF files.^19

What is CU-GR

Is a VLSI global routing tool.^20

What is Klayout

It helps with mask layouts. ^21